Faculty Development Program on VLSI Design and Modeling (Intensive Short Course)

13 May 2019

Report of FDP on VLSI Design and Modeling

By Vaibhav Nijhawan, Assistant Professor, ECE Department M.A.I.T.

Department of ECE, Maharaja Agrasen Institute of Technology (M.A.I.T) conducted a one week Faculty Development Program on “VLSI Design & Modeling (Short Intensive Course)”, which was held from 6th May. 2019 to 11th May 2019 at M.A.I.T campus.

This Faculty Development Programme (FDP) was aimed at honing the teaching and research skills of prospective, new and seasoned management teachers, researchers in the field of VLSI Design and Modeling.

The keynote speakers during the FDP were Prof. R.S.Gupta (ECE Department, MAIT), Dr. P.K. Saxena (Tech Next Lab Pvt. Ltd.), Dr. Yogesh Pratap (Delhi University) and Dr. Manoj Kumar

(Post Doctoral Fellow, Dept. of Electrical Engg., IIT Delhi). Lab sessions were taken by Mr. Harendra Kumar (Synopsis), Mr. Ankush Singh and Mr. Mayank Singh (CoreEL), Dr. Sonam  Rewari and Mr. Nitin Trivedi (M.A.I.T.).

The program was attended by 63 faculties/Research Scholars. 20 attendees were from different academic institutions like Delhi Technological University, Delhi University, IIIT Delhi and colleges affiliated to Guru Gobind Singh Indraprastha University.


Objectives of the Programme:

In the last few years, VLSI Design Technologies have gained immense popularity in the research community. The aim of this FDP is to provide research aspects and solutions to the various problems related to the VLSI Design & Modelling.

  1. To provide a comprehensive overview of the fundamental concepts as well as latest CAD TOOLS (Mentor Graphics & Silvaco).
  2. Focus on emerging concepts of VLSI Design & Modelling.
  3. To expand the in-depth knowledge of faculties, industry delegates.
  4. To generate more open problems for research in related areas.   


Topics covered:

  1. Evolution of Electronics & VLSI Design.
  2. Very large scale integration – Monolithic and Hybrid IC.
  3. VLSI Design isolation, Oxide isolation, Diode Isolation, Building blocks, Layout of Passive element.
  4. Resistor geometry, Power dissipation, Power density, Tolerance.
  5. Design of semiconductor diffused resistors, thin film resistor and Monolithic Capacitor. Fabrication of thick oxide MOSFET and CMOS.
  6. Design of Silicon Integrated circuits, Concept of buried layer, Initial Artwork, Isolation Diffusion.
  7. Analytical modelling of MOS Devices in VLSI, Deep sub-micron modelling, Advance MOSFET Design Structure.
  8. CMOS Digital IC Design, Threshold Voltage of Digital IC, Inverter Design.

Day 1 of FDP (Evolution of Electronics & VLSI Design)

Inauguration of the Programme was done by Prof.(Dr.) M.L. Goyal , Vice- Chairman, Academics MATES. Dr. Goyal had joined Maharaja Agrasen Institute of Technology, as its Director in September 2008.  He superannuated in September 2008 as General Manage, from CMC Limited, a Tata Enterprise.

Prof. R.S. Gupta delivered a talk on Evolution of Electronics & VLSI Design. He delivered an illuminating and inspiring lecture on very important aspects of VLSI Technology like VLSI overview, Design, Recent trends, Device Simulation, IC fabrication, embedded applications. He also discussed on “Challenges and advances of field effect transistors (FETs) for future integrated circuit applications”. Prof. R.S. Gupta is a Professor in the Electronics and Communication Engineering Department, Maharaja Agrasen Institute of Technology, Delhi. He is Life Senior Member IEEE. He was Chairman in IEEE-EDS Delhi Chapter (2007-2011).

In the afternoon session Mr. Harendra Kumar, from Synopsis gave a lab session on hands on experiments for different application in VLSI field.


Day 2 of FDP (VLSI Design isolation, Oxide isolation, Diode Isolation, Building blocks, Layout of Passive element.)

An informative lecture on “MICROELECTRONICS FABRICATION” was discussed by Prof. R.S.Gupta. During the lecture participants were learned Design of semiconductor diffused resistors, thin film resistor and Monolithic Capacitor along with Fabrication of thick oxide MOSFET and CMOS.

During the lab session Mr. Mayank Singh took a interactive session. His Agenda of the session was :-

a)       7-Series Architecture Overview

b)       Basic of vivado software

c)       Demonstration on Zed Board.

He gave hand on the vivado software. Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of HDL designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.Vivado represents a ground-up rewrite and re-thinking of the entire design flow (compared to ISE), and has been described by reviewers as "well conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive”.

Mr. Mayank did advance course from CDAC Noida with specialization in VLSI. He have worked with SONY Electronics in Technical department, and Presently working in CoreEL Technologies as Application Engineer & have 2+ year experience in VLSI – (Xilinx FPGA Kits & tools)


Day 3 of FDP ( CMOS Digital IC Design )

On the 3rd day Dr. Gupta delivered a lecture on Analytical modelling of MOS Devices in VLSI, Deep sub-micron modelling and Advance MOSFET Design Structure.In this session participants were taught CMOS inverter characteristics, noise margin and also the design of complex combinational logic circuit using CMOS.In this session participants realized the significance of static and dynamic circuits and their operation with precharge and evaluation phases.

In the lab session Mr. Ankur Sangal gave hand on the HEP-1 Design tool by mentor Graphics. In Session CMOS circuit design  and Layout simulations were performed.Analog and Digitals circuits were designed using the software.


Day 4 of FDP (Semiconductor Technology)

Dr. Praveen Saxena (Founder Director, CEO,CTO TNL Pvt. Lt. ) has delivered useful lecture to provides rapid and cost effective solution for overall semiconductor technology development through innovative Technology Computer Aided Design (TCAD) tools. He had a discussion on TNL framework is designed to innovate the semiconductor device designing. It accomodate atomistic based thin film growth simulator, full band simulator, material characterization simulator and Monte Carlo particle device simulator.

Day 5 of FDP (Low power VLSI/ULSI design applications)

Dr. Yogesh Pratap (Delhi University) delivered a presentation on the analytical modelling and simulation of Junctionless Nanowire Transistors for Low power VLSI/ULSI design applications. He also discussed  research also includes the study of various types of localised charges on novel FET structures.

In Evening session Dr. Sonam Rewari and Mr. Nitin Trivedi ,Electronics and Communication Engineering Department,Maharaja Agrasen Institute of Technology , has demonstrated on “SILVACO TCAD AND TANNER SPICE”. In this session participants were skilled with device simulation using Silvaco TCAD and circuit layout design using Tanner Spice with specific examples.


Day 6 of FDP Day 5 of FDP (Analytical Model)

Dr. Manoj Kumar on the day discussed the analytical modeling along with sizing and scaling concept. He explained the Double Gate  and Multigate Structures and their digital application during the session. Dr. Manoj Kumar is currently Post Doctoral Fellow at IIT Delhi.

VALEDICTORY SESSION: The honorable personalities present in this occasion were Prof.(Dr.) M. L. Goyal and Prof(Dr.) R.S. Gupta.  The Head of the Department of ECE, Dr. Sunil Kumar summarized the program. Certificate were Distributed to all the participants attended the programme.    All the personalities appreciated the department for organizing the FDP. The program was ended with vote of thanks by Dr. P.K. Sinha Co-Convener of the FDP.


 Download Brochure Program Schedule