Device Research Laboratory (DRL)

Block No.4, Room No. 402A, ECE Dept, MAIT

 

Thrust Areas

  • Compact Modelling Of Gate All Around (GAA) MOSFET.
  • Research of Innovative Device Architectures.
  • Reliability Analysis of MOSFET under stressful conditions.
  • Device Applications for various purposes.

Latest Device Architectures


Junctionless Double Surrounding Gate MOSFET

Gate Engineered Gate Stack Schottky Barrier Gate All Around MOSFET

Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET
The Device Research Laboratory (DRL) in the department of Electronics and Communication (ECE) is well equipped. It has two advanced servers and 8 computer system with latest configuration. In addition to all this there is one colour and two normal printers. There are two advanced simulators, one is Silvaco ATLAS 3D device simulator and the other one is Visual TCAD device simulator. The students are working on various devices such as:- Junctionless Double Surrounding Gate (JLDSG) MOSFET, Gate Engineered Gate Stack Schottky Barrier Gate All Around MOSFET and Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET. Also at present there is one DRDO project entitled "Analysis and Characterization of Silicon Gate All Around (GAA) nanowire MOSFET for ULSI circuit applications". In 2015 about 12 papers were published in International Journal and Conferences. In 2016 till 31st March7 have been published in International Journals and Conferences. Some Latest publications have been listed below.

Latest Publications

1. "Numerical Modeling of Subthreshold Region of Junctionless Double Surrounding Gate MOSFET (JDSG) ," Sonam Rewari, Subhasis Haldar, , Vandana Nath, S.S. Deswal, and R.S. Gupta., Superlattices and Microstructures Journal, vol. 90, pp 8-19, Feb 2016.
2. "Physics based analytical model for surface potential and subthreshold current of cylindrical Schottky barrier Gate All Around MOSFET with High-k Gate stack", Manoj Kumar, Subhasis Haldar, Mridula Gupta, and R.S. Gupta. Superlattices and Microstructures Journal, vol. 90, pp 215-226, Feb 2016.
3. DS-Schottky Barrier Cylindrical GAA MOSFET: Nanosensor for Biochips," Manoj Kumar, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Nanomaterials and Energy Journal, Vol. 5, Issue 1, Jan. 2016.
4. "Analytical Modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM-CSG)" which you submitted to International Journal of Numerical Modelling," Nitin Trivedi, Manoj Kumar, Subhasis Haldar, S. S. Deswal, and R.S. Gupta. (Accepted).
5. "Analytical Modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM-CSG)" which you submitted to International Journal of Numerical Modelling," Nitin Trivedi, Manoj Kumar, Subhasis Haldar, S. S. Deswal, and R.S. Gupta. (Accepted).
6. "AC Analysis Of Junctionless Double Surrounding Gate for Tera Hertz Applications "Sonam Rewari, Subhasis Haldar, , Vandana Nath, S.S. Deswal, and R.S. Gupta, International Conference On Commutation Techniques In Information and Communication Technologies, 11-13 March, 2016, GGSIPU, New Delhi, India.
7. "DMG Insulated Shallow Extension Cylindrical GAA Schottky Barrier MOSFET for Removal Of Ambipolarity: A Novel Approach", Manoj Kumar, Yogesh Pratap, Subhasis Haldar, Mridula Gupta, R.S.Gupta, INEC 9-12 May 2016, Chengdu, China (Accepted).